The invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having memory cells, which can be selected via first selection lines and second selection lines, whose first selection lines are subdivided into a first group and into a second group and which has address terminals for feeding in addresses, via which the first selection lines of the two groups can be addressed. The integrated memory has a first address path, via which the address terminals are connected to the first selection lines of the first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to the first selection lines of the second group and which has corresponding second lines and a second decoder circuit. In this case, the first decoder circuit performs decoding of addresses that are fed to it more rapidly than the second decoder circuit of the integrated memory.
One type of such integrated memories are the so-called Double Data Rate DRAMs (DDRxe2x80x94Dynamic Random Access Memories), in which the first selection lines are column select lines and the second selection lines are word lines. With each rising clock signal edge, a column address is transferred to the memory at its address terminals. Within the memory, a column select line is then activated with the applied column address and a column select line is activated with a column address which follows the applied column address. Two data words are processed simultaneously in each clock cycle. One of the data words has the respective column address that is present and the other data word has a column address which follows the former column address and is calculated therefrom. The second address is generated from the respective column address that is present by the second decoder circuit. Thus, in contrast to the first decoder circuit, the second decoder circuit does not carry out simple decoding of the applied column addresses but additionally address transformation by means of which the second column address derived from the address that is present is generated. Therefore, the second decoder circuit, via which the column select lines of the second group are addressed, has a more complex construction than the first decoder circuit, via which the column select lines of the first group are addressed. For this reason, the decoding by means of the first decoder circuit takes place more rapidly than the decoding by means of the second decoder circuit.
The invention is based on the object of specifying an integrated memory of the type described in which, despite the different decoding times of the first and second decoder circuits, when a column address is present at the address terminals, it is possible to obtain an activation time of approximately the same length for the first selection lines of the first and second groups.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of memory cells, first selection lines and second selection lines connected to the memory cells;
the first selection lines being divided into a first group and into a second group;
address terminals for feeding in addresses for addressing the first selection lines of the first and second groups;
a first address path connecting the address terminals to the first selection lines of the first group, and having corresponding first lines and a first decoder circuit;
a second address path connecting the address terminals to the first selection lines of the second group, and having corresponding second lines and a second decoder circuit;
the first decoder circuit being configured to decode addresses received therein more rapidly than the second decoder circuit; and
the first lines having a longer signal propagation time than the second lines.
In other words, the first lines of the first address path have a longer signal propagation time than the second lines of the second address path. The first address path contains the fast first decoder circuit and the slow first lines. The second address path contains the slow second decoder circuit and the fast second lines. Consequently, the different processing speed by the two decoder circuits is (at least partly) compensated for by the different signal propagation times of the first and second lines.
By way of example, the first selection lines may be column select lines and the second selection lines may be word lines of the memory. The opposite may also be true in other embodiments of the invention.
In accordance with an added feature of the invention, the first lines are longer than the second lines. Here, the different signal propagation times of the first and second lines are obtained by the different line lengths. According to another embodiment of the invention, the different signal propagation times may also be obtained by different conductivities of the lines, for example, with the first lines having a lower conductivity than the second lines.
In accordance with an additional feature of the invention, the second decoder circuit comprises the first decoder circuit and a transformation unit connected between the first decoder circuit and the first selection lines of the second group, the transformation unit generating transformed output signals from output signals of the first decoder circuit. In this embodiment, the second decoder circuit is formed with the first decoder circuit together with a transformation unit connected downstream of the latter. The transformation unit generates transformed output signals from the output signals of the first decoder circuit. This has the advantage that the components of the first decoder circuit do not have to be provided twice in the two address paths. Thus, in the case of the embodiment of the invention that was outlined last, parts of the two address paths correspond to one another.
In accordance with a concomitant feature of the invention, when an address is applied to the address terminals, one of the first selection lines of the first group is selected via the first address path and, at the same time, one of the first selection lines of the second group is selected via the second address path.
The first and the second decoder circuit may be constructed in a single-stage manner or in a multistage manner. They may be arranged in the respective address path either in a centralized manner, or that is to say in a block, or, in a manner subdivided in a plurality of stages, in a decentralized manner, or that is to say in a distributed manner.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.